Recent improvements in MOS semiconductor technology have resulted in advancement in large scale integrated circuit microprocessors. The latest generation of LSI microprocessors is an order to magnitude more powerful than the previous generation of microprocessors introduced 3 or 4 years ago. The latest generation of microprocessors has 16-bit data paths and 16-bit arithmetic capability, and such microprocessors directly address multiple-megabyte memories. In terms of functional capability and speed, such microprocessors will outperform all but the high end models of current 16-bit minicomputers.
LSI microprocessor design is now at the stage where better implementation techniques are required in order to control complexity and meet tight design schedules. One technique for achieving these goals is to use microprogramming for controlling the processor. Most of the traditionally claimed benefits of microprogramming, for example, regularity (to decrease complexity), flexibility (to ease design changes), and reduced design costs, apply to the implementation problems for current LSI microprocessor design.
Generally, a data processor performs a series of operations upon digital information in an execution unit according to a stored program of instructions. These instructions are often termed "macroinstructions" in order to avoid confusion with the microinstructions contained in the control store of the data processor. The microinstructions are often grouped into microinstruction routines in order to perform various macroinstructions. In order to implement certain macroinstructions, the sequence of the microinstructions is dependent upon one or more variables. For example, a macroinstruction which is implemented with an iterative type microinstruction sequence may employ a loop counter which is decremented and tested for zero before repeating the microinstruction routine. Thus, the branch to the beginning of the microinstruction routine is conditional on the loop counter not being equal to zero. Similarly, for a multiply macroinstruction using microinstructions to perform an add/shift algorithm, whether or not an addition will be performed prior to the shift is conditional on a bit in a shift register. Where the next microinstruction is dependent upon two variables or conditions, the data processor may have to select the next microinstruction address from as many as four possible branch destinations.
Often, two microinstruction routines may test for the same condition and converge upon a common branch destination routine if the condition being tested is TRUE but diverge to two unrelated branch destination routines if the condition is FALSE (or vice versa). If the branch control logic within the data processor allows two different conditional branch microinstructions to share a common branch destination, then the size of the control store can be minimized since the destination routine need not be duplicated within the control store.
In addition, data processors typically are designed to implement macroinstructions which are expressly conditioned on various condition code bits such that branching within the macroinstruction program memory is possible (for example, a branch on condition macroinstruction). In this case, the condition to be tested is specified by the op-code of the macroinstruction. Since usually several different conditions may be tested (branch if zero, branch if overflow, branch if carry, etc.), the size of the micro control store will be increased since separate microinstructions would ordinarily be required to process each of the different conditional type macroinstructions.
Thus, it should be appreciated by those skilled in the art that a data processor which includes conditional branch logic which permits different conditional branch type microinstructions to share some but not all branch destinations and which allows microinstruction routines for processing conditional type macroinstructions to be shared is a significant improvement over the prior art.